1. Field of the Invention
The present invention relates to a semiconductor circuit apparatus and its test method, the semiconductor circuit apparatus having a plurality of combinational circuits for executing various logical calculations and sequential circuits such as flip-flops for executing a full scan test to test functionalities of the combinational circuits.
2. Description of Related Art
Various techniques have been proposed to detect defects of a variety of LSI's (e.g., refer to Japanese Patent Publication No. 2628154, Japanese Patent Laid-open Publication No. H10-123223). As one of these methods, an ATPG (automatic test pattern generation) method is known, which uses a full scan test by flowing a predetermined test pattern to all flip-flops in a circuit under the conditions that the flip-flops can be controlled and the outputs thereof can be observed, thereby observing the operation result of each logical circuit.
With this method, however, if the number of measurement points is increased in order to improve a defect detection rate, the number of flip-flops for the measurement purposes and the number of external terminals for output observation are required to be increased, resulting in a bulky scale caused by a complicated structure and an increased circuit space.
In the following description, a circuit for executing a logical calculation of an input value and outputting a unique output value is called a “combinational circuit” as its generic concept, and a circuit such as a flip-flop including a time sequential transition operation is called a “sequential circuit” as its generic concept.
It is desired for recent LSI's to adopt the mechanism of stopping an unnecessary clock in order to reduce a consumption power. For this structure, more complicated logical circuits are combined to finely control the supply/stop of the clock by using a clock enable signal.
The above-described ATPG method using the full scan test performs two operations, a shift operation of flowing a test pattern to each flip-flop and a capture operation of finding an actual detect in the state that logical circuits perform a normal operation. In the shift operation, it is designed such that a clock is always input to each flip-flop to be scanned, whereas in the capture operation, a clock line is not controlled at all, but the clock is controlled only by a test pattern to be flowed in the shift operation.
However, if the clock line is provided with a complicated circuit for controlling clock enable in order to reduce a consumption power as described above, it is necessary to form a test pattern by considering logic of both a test pattern for supplying a clock and a test pattern for identifying a detect. This results in drawbacks such as complicated test patterns, the increased number of defects unable to be properly detected, and a longer time to prepare the test pattern, thereby causing decrease in efficiency in circuit design and increase of production cost.
FIG. 4 is a block diagram showing an example of the structure of an LSI circuit having control circuits for the above-described clock enable (so-called clock enablers).
In this figure, a combinational circuit 110 is a circuit made of a logical circuit group for executing predetermined logical calculations. Input and output stages of the combinational circuit are provided with flip-flops 121, 122, 123 and 124 and selectors 131, 132, 133 and 134 for selecting data input to the respective flip-flops 121, 122, 123 and 124 between a normal mode and a test mode. By switching the selectors 131, 132, 133 and 134, for example, data transfer is possible without passing through the combinational circuit 110 to and from the respective flip-flops 121, 122, 123 and 124.
Combinational circuits 141, 142, 143 and 144 are provided at the input stages of the flip-flops 121, 122, 123 and 124 to generate enable signals for the flip-flops 121, 122, 123 and 124. Clock enablers 151, 152, 153 and 154 are provided at the output stages of the combinational circuits 141, 142, 143 and 144 to control supply/stop of a clock to the flip-flops 121, 122, 123 and 124.
The combinational circuits 142 and clock enabler 152 control the flip-flops 121 and 122 at the input stage of the combinational circuit 110, and the combinational circuit 141 and clock enabler 151 control another flop-flop 125.
The combinational circuits 143 and 144 and clock enablers 153 and 154 are an example of a multi-stage circuit for controlling the flip-flops 123 and 124 at the output stage of the combinational circuit 110.
FIG. 5 is a block diagram showing a clock enabler to be used with the circuit shown in FIG. 4.
A clock enabler 210 is disposed between a combinational circuit 200 for generating an enable signal and a flip-flop (omitted in FIG. 5) for scan test. The clock enabler 210 is constituted of an OR circuit 211, a latch circuit 212 and an AND circuit 213. The OR circuit 211 generates an OR between an enable signal E output from the combinational circuit 200 and a shift scan control signal SE which is a timing signal in the shift operation. The latch circuit 212 latches an output signal from the OR circuit 211. The AND circuit 213 generates an AND between an output of the latch circuit 212 and a clock signal CK, as an enable clock signal ECK which is supplied to the enable input terminal of the flop-flop.